1. Field of the Invention
The present invention relates to methods of fabricating buried digit lines. Particularly, the present invention relates to a method of fabricating digit lines that are substantially free of stringers. More particularly, the present invention relates to a method of removing stringers from between the straps, plugs, and digit lines of semiconductor devices that include digit lines having widths of less than about 0.25 microns. The present invention also relates to semiconductor devices including buried digit lines that are substantially free of stringers and that have widths of less than about 0.25 microns.
2. Background of Related Art
Conventional semiconductor memory devices typically include an array of memory cells, each of which is in communication with a word line and a digit line. Due to the demand for semiconductor devices of ever-increasing density and ever-decreasing size, the semiconductor industry has sought ways to fabricate smaller, more compactly organized features. Thus, in semiconductor memory devices, the sizes of various features, as well as the spacing therebetween, have decreased. For example, the width of state of the art digit lines has decreased to about 0.25 microns or less. The spacing between adjacent digit lines has similarly decreased to about 0.30 microns or less.
Conventionally, photomask techniques, which typically employ visible to near infrared wavelengths of light, have been used to fabricate the digit lines of semiconductor memory devices. The sizes of features of such photomasks are, however, limited by the wavelengths of electromagnetic radiation employed to define these photomasks. As a result, the sizes and spacing of features defined either directly or indirectly by such photomasks are similarly limited.
Semiconductor memory devices that include digit lines having widths of less than about 0.25 microns and pitches of less than about 0.55 microns have been developed. The semiconductor memory devices, however, are relatively inefficient when compared with semiconductor memory devices having wider digit lines and pitches. The inefficiency of these more compact semiconductor memory devices is due, at least in part, to the potential for electrical shorts between adjacent digit lines. Electrical shorts in semiconductor memory devices with densely packed features may be caused by so-called xe2x80x9cstringersxe2x80x9d that remain following the definition of digit lines or other electrically conductive components, such as the plugs or straps that may be employed to link a contact to its corresponding digit line. The stringers may extend between adjacent structures or from a first structure to a location undesirably close to an adjacent, second structure. Thus, stringers may create an undesirable electrical path between adjacent digit lines.
Since semiconductor memory devices that include digit lines having widths of about 0.25 microns or less and digit line pitches of about 0.55 microns or less may include stringers that would likely cause electrical shorts between adjacent conductive structures, a significant percentage of the semiconductor memory devices will fail quality control testing. Consequently, fabrication costs are undesirably significantly increased.
Accordingly, there is a need for a method by which semiconductor memory devices that include digit lines with widths of less than about 0.25 microns and digit line pitches of less than about 0.55 microns may be more efficiently fabricated. There is a further need for a method of fabricating semiconductor memory devices of increased feature density which employs conventional techniques and equipment.
The present invention includes a method of fabricating semiconductor memory devices that include digit lines having widths of less than about 0.25 microns and, more particularly, to a method of fabricating semiconductor memory devices having digit lines that are at most about 0.18 microns wide. Through use of the method of the present invention, a semiconductor memory device may include digit lines that are spaced less than about 0.30 microns apart and, more preferably, at most about 0.22 microns apart. Thus, semiconductor memory devices fabricated in accordance with the method of the present invention may have a digit line pitch of less than about 0.55 microns and, more preferably, a digit line pitch of at most about 0.40 microns. The present invention also includes semiconductor memory devices fabricated in accordance with the method of the present invention.
In accordance with the method of the present invention, a bit contact region of a semiconductor memory device, which is disposed between adjacent word lines of the semiconductor memory device, may be doped as known in the art to define a bit contact. If a bit contact was not formed prior to the fabrication of structures on the substrate, the bit contact region may be exposed by known processes, such as mask and etch techniques, and the bit contact region doped, as known in the art. Alternatively, the exposed bit contact region may be doped following definition of the digit lines. As the conductive elements of the word lines between which the bit contacts are disposed may be exposed during exposure of the bit contact regions of the semiconductor memory device, a layer of insulative material, such as silicon oxide, may be disposed over the semiconductor memory device and adjacent the exposed conductive elements of the word lines. The layer of insulative material may be patterned to fabricate sidewall spacers that electrically isolate the conductive elements of the word lines from the trench within which the bit contact is disposed.
A layer of silicon nitride may be disposed over the semiconductor memory device, including over the bit contacts thereof, by known techniques. Such a layer of silicon nitride may be subsequently employed as an etch stop layer.
Layers of digit line material, such as polysilicon and tungsten silicide (xe2x80x9cWSixxe2x80x9d), may be fabricated or otherwise disposed over the layer of silicon nitride by known processes. A layer of insulative material may be disposed over the layer of tungsten silicide. A mask, such as a photomask, including a plurality of mutually parallel elongate apertures therethrough, may be defined over the semiconductor memory device. The elongate apertures of the mask are preferably aligned over rows of bit contacts and substantially perpendicular to the underlying word lines of the semiconductor memory device. Preferably, the apertures of the mask have a width that facilitates the definition of digit lines that are spaced less than about 0.30 microns apart and, more preferably, that facilitates the definition of digit lines that are spaced at most about 0.22 microns apart from one another. The distance between adjacent apertures of the mask preferably facilitates the definition of digit lines having a width of less than about 0.25 microns from the digit line material and, more preferably, facilitates the definition of digit lines that have a width of at most about 0.18 microns.
Digit lines may be defined through the mask by known etching processes. The etchants employed to define the digit lines may be selected based on their ability to remove the digit line material or materials. If a layer of insulative material was disposed over one of the layers of digit line material, a first etchant is preferably selected to etch the insulative material. Preferably, an etchant that will remove the silicon nitride etch stop layer is also employed to expose the bit contact regions. Preferably, isotropic wet etch processes are employed to facilitate the removal of electrically conductive stringers from between adjacent digit lines. As the digit lines are defined, digit line materials are removed from above the bit contact regions. If the use of a photomask is desired, two masks may be employed in these patterning processes so as to prevent distortion of the photomasks. A first mask could be employed to define the digit lines and cover the peripheries of the dice. A second mask could be employed to protect the digit lines and to remove any insulative material, digit line material or materials, and silicon nitride from the peripheries of the dice.
One or more layers of insulative material, such as silicon oxide, may be disposed or grown over the digit lines. If the layer or layers of insulative material are deposited onto the semiconductor memory device, such as by tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d) deposition techniques, another mask may be employed to define sidewall spacers adjacent the sides of each of the digit lines. Of course, the mask would be employed in combination with an etchant known to etch the insulative material in order to define the sidewall spacers therefrom. As the layer of insulative material may also cover bit contacts and any adjacent exposed conductive traces of word lines, sidewall spacers for the word lines may also be defined from the layer of insulative material. These sidewall spacers will serve to insulate the word lines from a stud or plug of conductive material to be disposed between the bit contacts and their corresponding digit lines.
Another mask may be employed to shield the bit contacts and the strap regions of the semiconductor memory device, which are disposed between the trenches within which the bit contacts are located and the digit lines that correspond to each of the bit contacts. This mask preferably abuts an exposed portion of a conductive element of a corresponding digit line. As the mask extends across the strap regions of the semiconductor memory device, the mask may protrude from the trenches and, therefore, from a surface of the semiconductor memory device. Preferably, a photomask is employed. Photoresist may be disposed over the surface of the semiconductor memory device and selected regions thereof exposed and developed to define a photomask. Due to the small dimensions of features such as the digit lines of the semiconductor memory device, and due to small dimensional tolerances, proper alignment of the mask is critical to the operability of the semiconductor memory device. Preferably, the photomask is hard-baked so as to facilitate the fabrication of features of desired shapes and dimensions.
A layer of insulative material may be disposed over the surface of the semiconductor memory device, including over regions of the semiconductor memory device that are covered by the photomask. Preferably, this layer of insulative material comprises silicon oxide. Thus, the layer of insulative material may be deposited onto the surface of the semiconductor device by known processes, such as by tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d) wet dip or other TEOS deposition processes. Preferably, the photomask is exposed through the layer of insulative material. If a TEOS wet dip is employed, the surface of the TEOS layer is preferably substantially planar and disposed in a thickness so that the photomask may be exposed through the TEOS layer. Alternatively, regions of a TEOS layer that overlie the photomask may be removed therefrom by known techniques, such as planarization (e.g., chemical-mechanical planarization or chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d)) techniques or mask and etch processes. As another alternative, the TEOS deposition process disclosed in U.S. Pat. No. 5,354,715, which issued to Wang et al. on Oct. 11, 1994, the disclosure of which is hereby incorporated in its entirety by this reference, may be employed to fabricate a layer of insulative material through which the photomask may be exposed.
The photomask may then be removed by known techniques. The semiconductor memory device may also be masked or otherwise cleaned.
Another layer of electrically conductive material, such as polysilicon, may be disposed over the semiconductor memory device within at least the strap regions thereof and in contact with at least the bit contacts thereof. A blanket isotropic etch-back of a type known in the art may be employed to reduce the height of the layer of conductive materialxe2x80x94preferably to about or just below the height of the digit lines. As electrically conductive studs and straps, which establish electrical communication between the bit contacts and their corresponding digit lines, are to be defined from this layer of electrically conductive material, another mask may be disposed over the semiconductor memory device to facilitate the substantial removal of any remaining conductive material or features from between adjacent conductive structures that are to be isolated from one another, as well as the definition of these features from the electrically conductive layer. Accordingly, the mask preferably shields quantities of electrically conductive material disposed over the bit contacts, which quantities of electrically conductive material are referred to herein as studs or plugs, as well as regions of the electrically conductive material within the strap regions. All other regions of the semiconductor memory device and, thus, the layer of electrically conductive material may be exposed through the mask. Electrically conductive material may be removed through the mask as known in the art, such as by the use of etchants. Preferably, the electrically conductive material exposed through these apertures is first etched with an anisotropic etchant, then with an isotropic etchant. The anisotropic etchant facilitates the definition of studs and straps of desired dimensions and removes any electrically conductive material between these features. The isotropic etchant further facilitates the substantial removal of any electrically conductive stringers that may remain from either the layer of electrically conductive material from which the studs and straps were defined or that may remain from the layer of digit line material from which the digit lines were defined.
A layer of insulative material, such as a silicon oxide, a glass, or silicon nitride, may be disposed over the semiconductor memory device, as known in the art, to insulate the exposed studs and straps. Additional structures may be fabricated over the digit lines of the semiconductor memory device.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.